2020-11-03 18:24:54 +01:00

22 lines
747 B
JSON

{
"version": "0.9",
"description": "Framework for Verilog RTL synthesis",
"homepage": "http://www.clifford.at/yosys/about.html",
"license": "ISC",
"url": "http://www.clifford.at/yosys/nogit/win32/yosys-win32-mxebin-0.9.zip",
"hash": "d638d860dff1f351c15ff0caeaa668742649677b874b1a9bdb0b6ce0e54840f5",
"extract_dir": "yosys-win32-mxebin-0.9",
"bin": [
"yosys.exe",
"yosys-abc.exe"
],
"checkver": {
"url": "http://www.clifford.at/yosys/download.html",
"regex": "yosys-win32-mxebin-([\\d.]+)\\.zip"
},
"autoupdate": {
"url": "http://www.clifford.at/yosys/nogit/win32/yosys-win32-mxebin-$version.zip",
"extract_dir": "yosys-win32-mxebin-$version"
}
}