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bit: Update to version 0.9.11

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This commit is contained in:
Jakub Čábera 2020-11-03 18:24:54 +01:00
parent 53a6cb8847
commit 528a695559
2 changed files with 8 additions and 8 deletions
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10
bucket/bit.json
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@ -1,16 +1,16 @@
{
"version": "0.9.10",
"version": "0.9.11",
"description": "Modernized git CLI",
"homepage": "https://github.com/chriswalz/bit",
"license": "Apache-2.0",
"architecture": {
"64bit": {
"url": "https://github.com/chriswalz/bit/releases/download/v0.9.10/bit_0.9.10_Windows_amd64.tar.gz",
"hash": "b9d117bca9f056407318dda6767db72fc2a92dc1ca53a7f4d3849129a8fb884a"
"url": "https://github.com/chriswalz/bit/releases/download/v0.9.11/bit_0.9.11_Windows_amd64.tar.gz",
"hash": "af129dc1c69a03d33fe203cb8c43f9c47c5b017beafee26c2c5bb7494010534f"
},
"32bit": {
"url": "https://github.com/chriswalz/bit/releases/download/v0.9.10/bit_0.9.10_Windows_386.tar.gz",
"hash": "be7bf76d9ff3b0ed8d06956ea3161045172d109220bd71116721dae9bfa8a45b"
"url": "https://github.com/chriswalz/bit/releases/download/v0.9.11/bit_0.9.11_Windows_386.tar.gz",
"hash": "f091dfb7cf8d08d484abc1f0207913d5b7286dcf546ecf9e5686d9bb290b1bfb"
}
},
"bin": "bit.exe",

6
bucket/yosys.json
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@ -1,10 +1,10 @@
{
"version": "0.9",
"description": "Open source framework for Verilog RTL synthesis.",
"description": "Framework for Verilog RTL synthesis",
"homepage": "http://www.clifford.at/yosys/about.html",
"license": "ISC",
"url": "http://www.clifford.at/yosys/nogit/win32/yosys-win32-mxebin-0.9.zip",
"hash": "D638D860DFF1F351C15FF0CAEAA668742649677B874B1A9BDB0B6CE0E54840F5",
"hash": "d638d860dff1f351c15ff0caeaa668742649677b874b1a9bdb0b6ce0e54840f5",
"extract_dir": "yosys-win32-mxebin-0.9",
"bin": [
"yosys.exe",
@ -12,7 +12,7 @@
],
"checkver": {
"url": "http://www.clifford.at/yosys/download.html",
"regex": "yosys-win32-mxebin-([\\d.]+).zip"
"regex": "yosys-win32-mxebin-([\\d.]+)\\.zip"
},
"autoupdate": {
"url": "http://www.clifford.at/yosys/nogit/win32/yosys-win32-mxebin-$version.zip",