diff --git a/bucket/yosys.json b/bucket/yosys.json
index 444df38733..f70254c2f2 100644
--- a/bucket/yosys.json
+++ b/bucket/yosys.json
@@ -1,21 +1,14 @@
 {
     "version": "0.9",
     "description": "Framework for Verilog RTL synthesis",
-    "homepage": "http://www.clifford.at/yosys/about.html",
+    "homepage": "https://yosyshq.net/yosys/",
     "license": "ISC",
-    "url": "http://www.clifford.at/yosys/nogit/win32/yosys-win32-mxebin-0.9.zip",
+    "notes": "Separate binaries are no longer released for Yosys, but updated versions are included in OSS CAD Suite (versions/oss-cad-suite-nightly)",
+    "url": "https://github.com/ScoopInstaller/Binary/raw/master/yosys/yosys-win32-mxebin-0.9.zip",
     "hash": "d638d860dff1f351c15ff0caeaa668742649677b874b1a9bdb0b6ce0e54840f5",
     "extract_dir": "yosys-win32-mxebin-0.9",
     "bin": [
         "yosys.exe",
         "yosys-abc.exe"
-    ],
-    "checkver": {
-        "url": "http://www.clifford.at/yosys/download.html",
-        "regex": "yosys-win32-mxebin-([\\d.]+)\\.zip"
-    },
-    "autoupdate": {
-        "url": "http://www.clifford.at/yosys/nogit/win32/yosys-win32-mxebin-$version.zip",
-        "extract_dir": "yosys-win32-mxebin-$version"
-    }
+    ]
 }